发明名称 |
Method and system for fast ethernet serial port multiplexing to reduce I/O pin count |
摘要 |
A system and method of reducing the input and output pins used to interface a fast serial port Ethernet processing system using multiplexing. Using the system of the present invention, four pins can allow a plurality of Ethernet communication paths to be connected to a single processor on a substrate. These four connections include a clocking input as well as a strobe signal which coordinates the multiplexing and identifies the time period for a predetermined source. The physical layer and the processor are each provided with a multiplexor which is controlled by the strobe to select the network to be coupled at any given time. The multiplexor includes a counter which is incremented by the clocking input and reset by the strobe signal.
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申请公布号 |
US2001050921(A1) |
申请公布日期 |
2001.12.13 |
申请号 |
US20010834591 |
申请日期 |
2001.04.13 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BARKER KENNETH JAMES;HOFFMAN CHARLES REEVES |
分类号 |
H04L12/56;(IPC1-7):H04J3/16 |
主分类号 |
H04L12/56 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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