| 摘要 |
The present invention relates generally to data processing systems, in particular, to computer-controlled automatic test systems for testing integrated circuits, and more particularly to memory test systems which interface with high speed protocol memories such as synchronous DRAM, in particular DDR.A data processing system comprises a data transmitter having a plurality of data transmitting sections operable in parallel for transmitting data, wherein the data trasmitter additionally comprises a circuit for synchronising said parallel data transmitting sections; a programmable frequency clock generator for generating a clock signal, wherein said programmed frequency includes a full-frequency and a low-frequency, the low frequency being a quotient of the full frequency and a number of said data transmitting sections; a multiplexer that receives data from said data transmitting sections at said low frequency and provides multiplexed output data at said full frequency; a plurality of registers for latching data and supplying latched data to a plurality of logic devices; wherein said data transmitting sections, said registers and said receiving devices operate at said low frequency; while said output data are transmitted and received at said full frequency. |
