发明名称 Memory testing method and memory testing apparatus
摘要 A memory testing method and apparatus are provided, which can test in short time a flash memory. In case of testing a flash memory having block function, in a memory testing method and apparatus in which a predetermined logical value is written in memory cells constituting each of blocks of the memory, the written logical value is read out from the memory cells to compare it with an expected value, and a decision that, when the read-out logical value and the expected value do not coincide with each other, such memory cell is a failure memory cell, a decision is rendered that, when the number of failure memory cells in each block reaches a predetermined number, such block is a bad block, and the test of such block is stopped. In addition, a decision is rendered that, when the number of failure memory cells on the same address line reaches a predetermined number, such address line is a bad address line, and after such decision has rendered, the test of memory cells on the bad address line is substantially not effected.
申请公布号 US2001052093(A1) 申请公布日期 2001.12.13
申请号 US20010844301 申请日期 2001.04.27
申请人 JAPAN AVIATION ELECTRONICS INDUSTRY LIMITED 发明人 OSHIMA HIROMI;OKINO NOBORU;KAWATA YASUHIRO
分类号 G01R31/28;G06F11/22;G06F12/16;G11C16/06;G11C29/00;G11C29/44;G11C29/56;(IPC1-7):G06F11/00 主分类号 G01R31/28
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