发明名称 |
Method for simultaneously forming a storage-capacitor electrode and interconnect |
摘要 |
A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes at least one and preferably two capacitor electrodes for making both types of interconnects. A method for making the DRAM memory cell includes forming one or more capacitor electrodes at the same time the electrodes of the storage capacitor of the memory cell are formed, and from the same material as the storage capacitor electrodes.
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申请公布号 |
US2001050385(A1) |
申请公布日期 |
2001.12.13 |
申请号 |
US20010750790 |
申请日期 |
2001.01.02 |
申请人 |
KOTECKI DAVID E.;RADENS CARL J.;GAMBINO JEFFREY P.;BRONNER GARY B. |
发明人 |
KOTECKI DAVID E.;RADENS CARL J.;GAMBINO JEFFREY P.;BRONNER GARY B. |
分类号 |
H01L21/8242;(IPC1-7):H01L21/336;H01L27/108;H01L29/76;H01L29/94;H01L31/119 |
主分类号 |
H01L21/8242 |
代理机构 |
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代理人 |
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地址 |
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