发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT AND CLOCK DISTRIBUTION CIRCUIT
摘要 <p>A clock transmission system contains a plurality of first clock buffers (4) two or more of which are connected in series and which receives/outputs complementary clock signals, second clock buffers (6) each complementary clock signal outputted by the last one of the first clock buffer and outputting a single-phase clock signal, and third clock buffers (9) two or more of which are connected in series and which transmits the single-phase clock signal from the second clock buffer. Since AC noise carried on the complementary clock signal is in-phase noise, it is cancelled by the differential amplification by a complementary clock buffer constituted of three or more buffers: the first clock buffers and the second clock buffer arranged in the complementary clock signal transmission paths. The relation between the numbers of first and second clock buffers and that of third clock buffer solves the trade-off between the prevention of malfunction due to dynamic skew and the increase of the circuit size and of generated heat due to the prevention.</p>
申请公布号 WO2001095075(P1) 申请公布日期 2001.12.13
申请号 JP2000003578 申请日期 2000.06.02
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