| 摘要 |
<p>A multiplication of digital data by small-scale and low-power consumption circuits. ANDs of all combinations of the respective bits of first digital data and the respective bits of second digital data are generated. A capacitive coupling is configured by a plurality of capacitances each having a capacity proportional to the sum of weights of pair of bits corresponding to each AND, an output of the capacitive coupling is connected to an inverting amplifier, and a multiplication result is output as analog data. <IMAGE></p> |
