发明名称 |
Pairing of micro instructions in the instruction queue |
摘要 |
An apparatus and method are presented for increasing the throughput within a single-channel of a pipeline microprocessor. Back-to-back pairs of micro instructions are evaluated to determine if they can be combined for execution in parallel. If so, then they are combined and issued for concurrent execution. The apparatus includes a micro instruction queue that buffers and orders micro instructions for sequential execution by the pipeline microprocessor. Within the micro instruction queue, a second micro instruction is ordered to execute immediately following execution of a first micro instruction. Pairing logic is coupled to the micro instruction queue. The pairing logic combines the first and second micro instructions so that the first and second micro instructions are executed in parallel by the pipeline microprocessor.
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申请公布号 |
US6330657(B1) |
申请公布日期 |
2001.12.11 |
申请号 |
US19990313907 |
申请日期 |
1999.05.18 |
申请人 |
IP-FIRST, L.L.C. |
发明人 |
COL GERARD M.;HENRY G. GLENN |
分类号 |
G06F9/28;G06F9/318;G06F9/38;(IPC1-7):G06F9/30;G06F9/40 |
主分类号 |
G06F9/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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