Methods for fabricating a multilevel interconnection for an integrated circuit device utilizing a selective overlayer

摘要

The present invention utilizes a selective overlayer to provide more efficient fabrication of a dual damascene multilevel interconnect structure. The selective overlayer serves as a protective mask which prevents the upper layer of the composite layer from being eroded during the formation of the multi-level interconnects. The present invention also solves some of the problems associated with the full-via first and partial-via first fabrication methods because the selective overlayer enables an efficient, deep partial via to be formed while preventing the deposit of undeveloped photoresist in subsequent fabrication steps. The present invention also provides advantages during the planarization and polishing of the dual damascene structure after the deposition of the conductive layer because the selective overlayer allows for efficient planarization without loss of trench depth control.