| 摘要 |
An electronic system, such as a video decoder (80), includes a clock generator circuit (22, 22') based upon a phase-locked loop (PLL) (25). The PLL (25) includes a voltage controlled oscillator (VCO) (30) that produces a plurality of evenly-spaced output phases, each of a locked frequency relative to a reference clock (CREF). A frequency synthesis circuit (27) receives a frequency selection value on control lines (FREQ) that include an integer and a fraction portion. The integer and fraction portion of the frequency selection value are added to the current contents of a register (40) that stores the previous integer value used to select the corresponding phase from VCO (30) for application to the clock input of a toggle flip-flop (36) from which the output clock (COUT) is generated. Use of the fraction portion permits a time-averaged clock frequency to be produced with more precision than the multiple phases output by the VCO (30). Alternative embodiments include multiple frequency synthesis circuits (27) based upon the same PLL (25), and the generation of a phase-shifted secondary output from a phase synthesis circuit (29) that is slaved to the frequency synthesis circuit (27). Additional performance is obtained by providing separate paths (52a, 52b) for producing the leading and trailing edges of the output clock (COUT).
|
