Semiconductor memory device having write data line

摘要

A write control circuit of a DRAM core cell includes a sense amplifier and first to third N channel MOS transistors. The first and third MOS transistors constitute a column selection gate. If data "1" is written, a write mask signal and a data line are set at L level to render the second MOS transistor nonconductive. If data "0" is written, the write mask signal and the data line are set respectively at L and H levels to render the second MOS transistor conductive. In order to inhibit data rewriting, the write mask signal and the data line are both set at H level to render the second and third transistors nonconductive. Layout area and power consumption can be reduced compared with the conventional approach which requires two data lines.