Level-shifter for extremely low power supply

摘要

An improved level shifter circuit is provided which is designed for use with an extremely low power supply voltage. The level shifter circuit includes a fourth NMOS transistor, a third PMOS transistor, and a fifth NMOS transistor connected in series and interconnected between the high voltage and the output terminal. As a result, the high voltage will still be passed to the output terminal when the high voltage is lowered to be equal to the low power supply voltage.