Method for laterally peaked source doping profiles for better erase control in flash memory devices

摘要

A system and method for controlling a characteristic of at least one memory cell on a semiconductor is disclosed. The at least one memory cell includes a gate stack, a source, and a drain. The semiconductor includes a surface. In one aspect, the method and system include providing the gate stack on the semiconductor and providing the source including a source dopant having a local peak in concentration. The local peak in concentration of the source dopant is located under the gate stack and in proximity to a portion of the surface of the semiconductor. In another aspect the method and system includes a memory cell on a semiconductor. The semiconductor includes a surface. The memory cell includes a gate stack on the semiconductor, a source, and a drain. The gate stack has a first edge and a second edge. The source is located in proximity to the first edge of the gate stack. The drain is located in proximity to the second edge of the gate stack. A first portion of the source is disposed under the gate stack. The source includes a source dopant having a local peak in concentration of the source dopant. The local peak in concentration of the source dopant is located under the gate stack and in proximity to a portion of the surface of the semiconductor.