发明名称 |
Clock input buffer with noise suppression |
摘要 |
A circuit is designed with a delay circuit (300) coupled to receive a clock input signal (CLK) and a control signal (DFT). The control signal has a first logic state and a second logic state. The delay circuit produces a clock control signal (*CLK) at a first time in response to the first logic state and at a second time in response to the second logic state. A clock circuit (200) is coupled to receive the clock input signal and is enabled by the clock control signal. The clock circuit produces a first clock pulse signal having a predetermined width in response to a first transition of the clock input signal and produces a second clock pulse signal having the predetermined width in response to a second transition of the clock input signal.
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申请公布号 |
US6329867(B1) |
申请公布日期 |
2001.12.11 |
申请号 |
US19990390741 |
申请日期 |
1999.09.07 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
PENNEY DANIEL B.;WALDROP WILLIAM C.;BROWN JASON M. |
分类号 |
G11C7/10;G11C7/22;G11C11/4076;G11C11/4093;H03K5/1534;(IPC1-7):H03K17/28;H03K17/296 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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