Tristate output buffer with matched signals to PMOS and NMOS output transistors

摘要

A circuit comprising a first and a second circuit. The first circuit may be configured to generate a first control signal and a second control signal in response to (i) a first input signal and (ii) an enable signal. The first control signal generally matches the second control signal. The second circuit may be configured to generate a third control signal and a fourth control signal in response to (i) a second input signal and (ii) the enable signal. The third control signal generally matches the fourth control signal.