发明名称 LAYOUT DESIGN METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT AND LAYOUT DESIGN EQUIPMENT
摘要 PROBLEM TO BE SOLVED: To provide the layout design method of a semiconductor integrated circuit and a layout design equipment capable of highly precisely and automatically predicting the area of an analog circuit or the area of an analog and digital mixed integrated circuit without performing layout design after circuit design. SOLUTION: The layout design equipment is provided with an element judging means 6 for judging the kind of an element composing a soft block and outputting element judging information to an element area predicting means 7, and the element area predicting means for referring to the element judging information and element characteristic information, predicting the area of the element every element and outputting predicting element area information. A circuit block area predicting means 8 refers to the predicting element area information, the area information of a hard block and wiring margin information, the predicting circuit block area of the soft block is calculated, and a chip area predicting means 9 refers to the predicting circuit block area to calculate a predicting chip area.
申请公布号 JP2001338980(A) 申请公布日期 2001.12.07
申请号 JP20000156291 申请日期 2000.05.26
申请人 NEC MICROSYSTEMS LTD 发明人 KOJIMA NORIKO
分类号 G06F17/50;H01L21/82;(IPC1-7):H01L21/82 主分类号 G06F17/50
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