发明名称 DELAY LOCKED LOOP CIRCUIT
摘要 PURPOSE: To reduce circuits corresponding to respective panels and to reduce the number of required parts by allocating upper/lower display areas of a DSTN panel to a panel of another module and controlling two displays with a device driver for circuit/OS controlling one sheet of panel. CONSTITUTION: A video controller(20) outputs DSTN controlling signals of control signals and display data signals (chrominance signals) (31, 33) to control one sheet of panel. For driving half-sized panels (41, 42), when these control signals and a chrominance data signal (31) for an upper panel or the chrominance data signal 33 for a lower part panel exist, the panels are displayed. Then, the signal lines of the chrominance data signal (31) for the upper part panel and the chrominance data signal (33) for the lower part panel are connected respectively to the half-sized panels (41, 42). Further, the control signal originally being a piece is divided into two signals (37, 39) on the way to be connected to respective panels, and two sheets of panels (41, 42) are driven.
申请公布号 KR20010006631A 申请公布日期 2001.12.07
申请号 KR20000027471 申请日期 2000.05.22
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