| 摘要 |
PROBLEM TO BE SOLVED: To reduce the number of PEPs, improve throughput, and reduce the cost by simultaneously implanting impurities into a capacity region and each region of the source and drain of each N-type and P-type TFT, by utilizing features that an original impurity conductivity-type stays even if an opposing impurity is implanted into an already implanted impurity region in the manufacturing process of a TFT array. SOLUTION: A polysilicon layer 2 is patterned to a P-channel TFT region 11, an N-channel TFT region 12, and a capacity region 10 on a glass substrate 1, a gate oxide film 3 is formed on it, resist is patterned to all of the P-channel TFT region 11 and on the gate region of the N-channel TFT region 12, P6 is subjected to ion doping with the resist as a mask, the resist is removed, then gate metal is patterned to the gate part of the P-channel TFT region 11, the channel region of the N-channel TFT region 12, and the capacity region 10 for generation, an opposing impurity B7 is ion-doped with the gate metal as a mask to manufacture the TFT array, thus eliminating a PEP process.
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