发明名称 |
SIMULATED DEFECT WAFER AND METHOD FOR FORMING DEFECT INSPECTION RECIPE |
摘要 |
PROBLEM TO BE SOLVED: To provide a method for forming independently of a proficiency of a former an optimum defect inspection recipe whereby all kinds of defects can be detected. SOLUTION: A temporary inspection recipe is formed with the use of the simulated defect wafer 1 including simulated defect patterns DF1-DF3 having a change in a height direction and a change in a plane shape to a simulation normal pattern. Defect inspection of the simulated defect wafer 1 is carried out. Detected defect data are compared with preliminarily obtained simulated defect data of the simulated defect wafer 1 to quantify a defect detection sensitivity. Recipe parameters are changed until a desired defect detection rate is obtained. The temporary inspection recipe is thus formed. |
申请公布号 |
JP2001337047(A) |
申请公布日期 |
2001.12.07 |
申请号 |
JP20000160506 |
申请日期 |
2000.05.30 |
申请人 |
TOSHIBA CORP |
发明人 |
NODA TOMONOBU |
分类号 |
G01B21/30;G01N21/956;H01L21/66;H01L23/544;(IPC1-7):G01N21/956 |
主分类号 |
G01B21/30 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|