FORMING METHOD OF SHALLOW TRENCH ISOLATION REGION OF MOS TRANSISTOR

摘要

PROBLEM TO BE SOLVED: To provide the forming method of STI easy to achieve high speed by suppressing the rapid increase of electric power consumption while suppressing the lowering of a latch-up tolerated dose without employing next generation alignment technology in a semiconductor device including a MOS transistor. SOLUTION: A shallow trench 6a shallower than a shallow trench 3 is formed in the neighborhood of an element formation region 2a in STI comprising the shallow trench 3.