发明名称 TEST-FACILITING CIRCUIT FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To dispense with a self-test circuit, composed of a linear feedback shift register(an LFSR) which is required, in addition to an inspected circuit to reduce a circuit area by dispensing with a built-in data compression circuit for executing a self-test for the inspected circuit, in a semiconductor integrated circuit. SOLUTION: In this test faciliting circuit, the LFSR is composed of scan flip-flops 107 arranged regularly in a scan chain 109, an output value from the inspected circuit 101 are pattern-compressed, and signature is scanned in the scan chain 109 as a pseudo-random number sequence.
申请公布号 JP2001337136(A) 申请公布日期 2001.12.07
申请号 JP20000158760 申请日期 2000.05.29
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SUZUKI TAKEO;SUGANO MASAHIDE;KAJIMOTO YASUHIKO;TANAKA YASUHIRO;YOKOYAMA KENJI;HASHIMOTO SHINICHI;TAKETAZU HIROKUNI;FUKAZAWA HIROKIMI
分类号 G01R31/28;H01L21/822;H01L27/04;(IPC1-7):G01R31/28 主分类号 G01R31/28
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