| 摘要 |
<p>The digital-analogue converter receives a succession of bits y(k) of a binary signal and delivers, by sampling at a clock signal (H) rate, a positive (+Iref) or negative (-Iref) current according to the bit state of input. It comprises a circuit for the control of time of output current settling, comprising a capacitor (C0) and a circuit for charging one capacitor (C0,C0') at constant current up to a reference voltage (+V0,-V0), and the settling time is equal to the sum of charging time and discharging time. The current of charging and discharging of capacitor is directed to an output load comprising a resistor and a capacitor in parallel (Rb,Cb), by means of interrupters (T1,T2,T3,T4) and current mirrors with transistors (Q7,Q8,Q9,Q10). In the first embodiment, the control circuit comprises an interrupter controlled by a clock signal, where the interrupter is connected between a positive supply terminal and a constant current source, a capacitor, a transistor and an operational amplifier with positive input connected to a reference potential. In the second embodiment, the control circuit comprises two interrupters in series with constant current sources, a capacitor connected to the joining point of interrupters, two transistors with the bases controlled by outputs of operational amplifiers, and positive inputs connected to two reference voltages. In the third embodiment, the control circuit comprises a circuit for charging and discharging of a capacitor (C0,C0') with constant current between two reference voltages (+V0,-V0), where the capacitor (C0) is connected to the joining point of two transistors (Q5,Q6), an operational amplifier (71) with positive input connected to a given potential (VG), two current mirrors with common output, which is the output of converter, the first pair of interrupters (T1,T2) connected to the first current mirror with transistors (Q7,Q8), the second pair of interrupters (T3,T4) connected to the second current mirror with transistors (Q9,Q10), and the two circuit branches are controlled by the clock signal (H) in opposition so that when the capacitor (C0) is charged, the capacitor (C0') is discharged. The circuits for charging and discharging of capacitors (C0,C0') use the same constant current sources (SC1',SC2'). The output current of converter is directed to a filter (Rb,Cb) as a load. The binary input y(k) of converter is obtained from a sigma-delta converter.</p> |
