| 摘要 |
PROBLEM TO BE SOLVED: To reduce the data amount of errors generated among repeatedly arranged cells in the DRC verification of the layout data of a semiconductor memory. SOLUTION: The information of cells being the origin of the generation of errors is added to error data as property, and the error data having the same property are extracted, and one of the error data is selected and registered as a new cell, and information is repeatedly added so that error data amount can be reduced.
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