发明名称 FAILURE ANALYSIS METHOD OF SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide an effective etching method for performing the failure analysis of LSI. SOLUTION: In the failure analysis method of a semiconductor device for a failure cause made by wiring formed on a semiconductor silicon board, a layer insulation film 3 is etched and removed on the semiconductor silicon board by using etching gas (for instance, CHF3) having a high etching selection ratio between a lower layer wire 2 and upper layer wiring 4, and the failure cause (foreign matter 5) is analyzed.
申请公布号 JP2001338961(A) 申请公布日期 2001.12.07
申请号 JP20000159712 申请日期 2000.05.30
申请人 SANYO ELECTRIC CO LTD 发明人 KANEKO MAMORU;ITABASHI ATSUSHI
分类号 H01L21/66;H01L21/302;H01L21/3065;(IPC1-7):H01L21/66;H01L21/306 主分类号 H01L21/66
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