PHASE/FREQUENCY DETECTOR FOR DEJITTER APPLICATIONS

摘要

A phase/frequency detector includes two D-Q flip-flops (102, 104), an OR gate (106), and an exclusive NOR (XNOR) gate (108). The phase/frequency detector is used in conjunction with a clock dejitter PLL where the underflow and overflow flags from a FIFO are coupled to the inputs of the OR gate and the Q outputs of the flip-flops are coupled to the inputs of the XNOR gate. When the phase is locked, the output of the XNOR has a 50 % duty cycle which causes the voltage across the filter to remain constant which maintains a steady VCXO output frequency. The FIFO will either underflow or overflow if the recovered clock and the VCXO run at different speeds. In this case, the flip-flops generate correction pulses that will drive the PLL filter voltage to the point where the VCXO is running at the correct frequency.