发明名称 |
REDUNDANCY ANALYSIS METHOD AND APPARATUS FOR MEMORY TESTING |
摘要 |
A method of determining a redundancy solution for a semiconductor memory under test (DUT) having redundant rows and columns is disclosed. The method includes the steps of first testing the DUT in a first environment with a first tester to generate a first fail data set. The first fail data set is then transferred to a second tester where the DUT is test in a second environment to generate a second fail data set. The first and second failure data sets are then merged to create a merged fail data set. A highly optimized redundancy solution is then determined based on the merged fail data set.
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申请公布号 |
WO0193276(A1) |
申请公布日期 |
2001.12.06 |
申请号 |
WO2001US15783 |
申请日期 |
2001.05.16 |
申请人 |
TERADYNE, INC. |
发明人 |
MICHAELSON, STEVEN, A.;YAFFE, ARTHUR;OLSTER, DANIEL;HONG, SUNG |
分类号 |
G11C29/00;G11C29/44;H01L21/66;(IPC1-7):G11C29/00;G06F11/20 |
主分类号 |
G11C29/00 |
代理机构 |
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地址 |
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