Method for testing a multiplicity of word lines of a semiconductor memory configuration

摘要

A method for testing a multiplicity of word lines of a semiconductor memory configuration in a multiple word line wafer test is described. To prevent a pulling-up of inactive word lines which are at a negative voltage when the active word lines are ramped down, the inactive word lines are decoupled from the negative word line voltage and are connected to a high impedance shortly before the active word lines are ramped down.