| 摘要 |
<p>A power detecting circuit with high performance suitably fabricated in a monolithic cuicit, suitably operated in a wide high-frequency range, having a detection characteristic the linearity of which is excellent and which varies little with the bias variation and the FET threshold voltage variation, having a small DC offset, and producing a balanced output. The power detecting circuit has two transistors (FET) (Q101, Q102) connected with a resistor element (R103) as a current source at a connection point of the sources and having almost the same characteristics. Almost equal gate bias voltages are supplied to the gates by gate bias supplying circuits (102, 103), and almost equal drain bias voltage is supplied to the drains. Capacitors (C102, C103) having almost equal and sufficiently large capacitances are connected. A high frequency signal RFin is supplied to the gate of the transistor (Q101). The difference in voltage between the drains are used as a detection output. A demodulator comprising such a power detection circuit is also disclosed.</p> |
