A multiple matchline sense circuit for detecting a single, more than one, or no match conditions during a search-and-compare operation of a content addressable memory is disclosed. The circuit compares the rising voltage rate of a multiple matchline to the rising voltage rate of a reference multiple matchline in order to generate a multibit result representing one of the three conditions. The circuit generates a self-timed control signal to end the search-and-compare operation, and to set the circuit to a precharge state.
申请公布号
WO0193274(A1)
申请公布日期
2001.12.06
申请号
WO2001CA00797
申请日期
2001.05.31
申请人
MOSAID TECHNOLOGIES INCORPORATED;MA, STANLEY, JEH-CHUN;MA, PETER, P.