A system and method for reducing timing mismatch in sample and hold circuits using the clock

摘要

The present invention relates to a high speed sample and hold circuit which comprises a plurality of sample and hold subcircuits coupled in parallel between an input and an output. The circuit also comprises a calibration circuit coupled to the plurality of sample and hold subcircuits. The calibration circuit is operable to establish a timing relationship between a hold signal and a clock signal for each of the plurality of sample and hold subcircuits which is generally the same. The established timing relationship reduces a timing mismatch between the plurality of sample and hold subcircuits and distortion associated therewith. The present invention also comprises a method of reducing timing mismatch in a high speed, parallel coupled sample and hold circuit. The method comprises synchronizing a hold signal to a clock signal by modifying the hold signal for each of a plurality of sample and hold subcircuits within the sample and hold circuit and utilizing the modified hold signals in the sample and hold subcircuits, respectively. <IMAGE>