| 摘要 |
A simplified clock control circuit in which noise and consumed electric power is reduced. When an output signal of a first flip-flop becomes "H" by input of a starting signal, an output signal of a first gate becomes "H", and a master clock signal given to a second gate is output as a clock signal. The clock signal is counted by a counter, and when the count value becomes a first set value, a trigger signal for starting another clock control portion is output from a first comparator. When the count value becomes a second set value, an operation end signal is output from a second comparator, an output signal of a second flip-flop becomes "L", and the output signal of the first gate becomes "L", to stop output of the clock signal.
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