发明名称 |
Methods of forming integrated circuit memory devices using masking layers to inhibit overetching of impurity regions and conductive lines |
摘要 |
Methods of forming integrated circuit memory devices may include steps to form memory cell access transistors therein. These steps may include steps to form a gate line on a semiconductor substrate and then implant dopants of first conductivity type into the semiconductor substrate to define a self-aligned impurity region therein. A spacer layer of a first material is then formed on a sidewall and upper surface of the gate line. An interlayer insulating layer of a second material is then formed on the spacer layer. A series of selective etching steps are then performed using different etchants. For example, a step is performed to selectively etch the interlayer insulating layer to define a contact hole therein, using the spacer layer as an etching mask to protect the gate line from etching damage. A selective etching step is then performed to convert the spacer layer into a sidewall spacer on the sidewall of the gate line. This etching step is performed using the interlayer insulating layer as an etching mask. A conductive plug (e.g., bit line plug) is then formed in the contact hole. This conductive plug forms an ohmic contact with the impurity region.
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申请公布号 |
US6326270(B1) |
申请公布日期 |
2001.12.04 |
申请号 |
US19990419836 |
申请日期 |
1999.10.15 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
LEE KANG-YOON;KANG WOO-TAG;KIM JEONG-SEOK;SHIN YOO-CHEOL |
分类号 |
H01L21/28;H01L21/60;H01L21/768;H01L21/8242;H01L27/108;(IPC1-7):H01L21/336 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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