| 摘要 |
A linear transform system (18) for decoding video data is provided. The system (18) includes inputs (50, 52, 54, 56, 58, 60, 62, 64) connected in series to a circuit (40) for implementing a decoding algorithm that includes a multiplication circuit stage (42, 44, 46) having a multiple output scaler structure (82, 84, 86). A bit-serial operator stage (48) is connected in series with the multiplication circuit stage (42, 44, 46). The bit-serial operator stage (48) is coupled to a plurality of outputs (66, 68, 70, 72, 74, 76, 78, 80) that generate decoded video data.
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