| 摘要 |
Vertical rate deflection signals are generated using a combination of digital and analog techniques. A signal is generated by a switched capacitor type accumulator circuit, a wave shape control circuit, and a DC signal centering circuit. The signal is periodically reset by initializing a first storage circuit in the accumulator circuit to an initial start voltage. A buffer couples the first storage circuit to a first signal output. A second signal output is produced by generating a controlled offset from the first signal output. The second signal output is sampled by a second storage circuit, and subsequently coupled to the first storage circuit. The amplitude and slope of the signal are determined by the controlled offset level. The wave shape control circuit dynamically controls the offset level. By varying the offset level, the waveform shape is adjusted to provide a linear ramp, S corrected ramp, EWPCC parabolic signal or the like. A look up table, multiplier and/or a DAC may be used with a controlled source to provide the controlled offset level. The output waveform is centered about a DC level by the signal centering circuit. The signal centering circuit samples the first signal output at half of the period of the vertical retrace signal, and subtracts the first signal output from the sampled signal to maintain an DC signal level for the ramp signal. The present invention provides for an economical, efficient, and simple method for generating vertical rate deflection signals.
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