COMPUTER-ASSISTED DESIGN ANALYSIS METHOD FOR EXTRACTING DEVICE AND INTERCONNECT INFORMATION

摘要

A method for extracting design information from a semiconductor integrat ed circuit (IC)or at least a portion thereof comprising the steps of: (a) imagi ng at least a portion of one or more IC layers to obtain stored images of said portions of the IC; (b) using manual or automatic registration techniques to mosaic images; (c) using an IC layou t package possessing a feature of allowing images to be displayed and moved and polygo ns to be created to allow the recreation of the IC layout in the form of polygons; (d ) exporting or storing of a polygon database in a standard IC layout format; (e) creating a table of transistor connections (netlist); (f) organizing circuit netlist into functional blocks of increasing complexity; and (g) generating a schematic diagram.