发明名称 |
Method of manufacturing an EPROM memory device having memory cells organized in a tablecloth matrix |
摘要 |
A method of manufacturing a semiconductor virtual ground memory device having a matrix of floating gate memory cells formed on a semiconductor substrate with a plurality of continuous bit lines extending across the substrate as discrete parallel stripes. The device also includes a circuit portion for selection transistors and decode and address circuit portions having P-channel and N-channel MOS transistors. According to the method, N-wells are formed in at least one substrate portion to accommodate the P-channel transistors, active areas of all transistors are defined using a screening mask, and then an isolation layer is grown through the apertures of the screening mask. The screening mask is not open over the matrix region of the memory cells.
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申请公布号 |
US6326266(B1) |
申请公布日期 |
2001.12.04 |
申请号 |
US19980141849 |
申请日期 |
1998.08.27 |
申请人 |
STMICROELECTRONICS S.R.L. |
发明人 |
BRAMBILLA CLAUDIO;CASSIO VALERIO;CAPRARA PAOLO;CREDA MANLIO SERGIO |
分类号 |
H01L21/8247;H01L27/105;(IPC1-7):H01L21/336;H01L29/778 |
主分类号 |
H01L21/8247 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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