Circuitry, architecture and method(s) for phase matching and/or reducing load capacitance, current and/or power consumption in an oscillator

摘要

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of clock signals each in response to (i) one or more control inputs and (ii) one or more of a plurality of phase timing elements. The second circuit may be configured to generate the plurality of phase timing elements.