发明名称 Trilayer/bilayer solder bumps and fabrication methods therefor
摘要 Solder bumps are fabricated by plating a first solder layer on an underbump metallurgy, plating a second solder layer having higher melting point than the first solder layer on the first solder layer and plating a third solder layer having lower melting point than the second solder layer on the second solder layer. The structure then is heated to below the melting point of the second solder layer but above the melting point of the first solder layer and the third solder layer, to alloy at least some of the first solder layer with at least some of the underbump metallurgy and to round the third solder layer. Accordingly, a trilayer solder bump may be fabricated wherein the first and third layers melt at lower temperatures than the second solder layer, to thereby round the outer surface of the solder bump and alloy the base of the solder bump to the underbump metallurgy, while allowing the structure of the intermediate layer to be preserved. Solder bump fabrication as described above may be particularly useful with lead-tin solder wherein the first solder layer is eutectic lead-tin solder, the second solder layer is lead-tin solder having higher lead content than eutectic lead-tin solder and the third solder layer is eutectic lead-tin solder. In yet other embodiments, the thickness and/or composition of the outer underbump metallurgy layer and/or of the first solder layer may be selected so that upon heating, sufficient tin from the first solder layer is alloyed with at least some of the outer underbump metallurgy layer, such that the first solder layer is converted to a fourth solder layer having the same lead content as the second solder layer. Bilayer solder bumps thereby may be provided.
申请公布号 AU6123401(A) 申请公布日期 2001.12.03
申请号 AU20010061234 申请日期 2001.05.07
申请人 UNITIVE ELECTRONICS, INC. 发明人 GLENN A. RINNE
分类号 H01L21/48;H01L21/60;H05K3/34 主分类号 H01L21/48
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