发明名称 FREQUENCY MULTIPLIER CIRCUIT
摘要 PROBLEM TO BE SOLVED: To generate a multiplied output, corresponding to the 2n-fold frequency of an input signal only through a digital circuit in a frequency multiplier circuit. SOLUTION: On the basis of a reference clock, for example, the cycle of an input signal A is counted by a counter circuit 13 of a cycle-measuring circuit part 11 and that count value C is latched by a latch circuit 14. Also, low-order 5-bit data Db of these latch data D and a count value E of a counter circuit 51 for performing count operation with a multiplied output from a counter circuit 43 as a clock are compared by a level comparator 21. According to the compared result, a data selector 31 is controlled, and the frequency-dividing ratio of the counter circuit 43 inside a frequency divider circuit 41 for dividing the frequency of the reference clock is switched over.
申请公布号 JP2001332962(A) 申请公布日期 2001.11.30
申请号 JP20000153384 申请日期 2000.05.24
申请人 TOSHIBA CORP 发明人 KOSAKA YOSHIAKI
分类号 H03K5/00;H03B19/00;(IPC1-7):H03K5/00 主分类号 H03K5/00
代理机构 代理人
主权项
地址