| 摘要 |
PROBLEM TO BE SOLVED: To solve the first problem that the speed of a vector instruction is suppressed since the flash processing of a cache is slower than the throughput of the storage processing of the vector instruction itself and the second problem that flash is performed even to data which are not the object of the flash since the data of plural bytes are registered to one cache line in a communication cache. SOLUTION: This processor is provided with a main storage means for storing the data, an instruction discrimination means for discriminating whether an effective object instruction is the vector instruction or not, an address generation means for generating an address in the main storage means for the processing data of the vector instruction when it is discriminated that it is the vector instruction by the instruction means, the storage register of the processing data and an instruction performance means for performing data transfer between the register and the address generated by the address generation means without performing cache flash.
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