BUFFER CIRCUIT BLOCK AND DESIGN METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE THE SAME

摘要

PROBLEM TO BE SOLVED: To easily provide, at high precision, a buffer circuit block as well as a design method for an LSI using it, for delay control of clock signal and transmission signal with a clock supply and signal transmission systems of LSI. SOLUTION: A library preparation step S10 is provided where a delay adjusting blocks are registered in a circuit library which comprise a plurality of buffer circuit blocks where the appearance, dimension, position of input/output terminal, input terminal capacity, drive capacity including load-dependency of an output part and the like of a block are identical with only a delay value different. There are further provided a first circuit design step S20, a first layout step S30, an actual wiring delay simulation step S40, a delay information extracting step S50, a first skew confirming step S60, a first skew adjusting step S70, a second skew confirming step S80, and a second skew adjusting step S90.