发明名称 HORIZONTAL SYNCHRONIZING SIGNAL SEPARATING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To improve stability in operation when the signal level of a composite synchronizing signal comes to a level lower than a prescribed level. SOLUTION: This horizontal synchronizing signal separating circuit is provided with a mask circuit 10 for masking a composite synchronizing signal CSYNC during a mask period set while being delayed from the transition timing of the composite synchronizing signal CSYNC and a PLL circuit 20 for generating a horizontal reference pulse, which is phase-locked on the basis of an output signal provided from the mask circuit 10 while defining a period excepting for this mask period as an output window of the composite synchronizing signal CSYNC, as a horizontal synchronizing signal. Especially, the mask circuit 10 is provided with an output inhibiting part for inhibiting a signal output in the state of making the composite synchronizing signal level lower than a specified level.
申请公布号 JP2001333294(A) 申请公布日期 2001.11.30
申请号 JP20000150252 申请日期 2000.05.22
申请人 TOSHIBA CORP 发明人 ANAI KIMIO
分类号 H04N5/10;H04N5/05;(IPC1-7):H04N5/10 主分类号 H04N5/10
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