发明名称 |
ERROR CORRECTION DECODER AND ERROR CORRECTION DECODING METHOD |
摘要 |
PROBLEM TO BE SOLVED: To provide an error correction decoder that can obtain desired transmission quality even when each signal sequence cannot completely be separated at once. SOLUTION: A decoder 211 applies error correction decoding to an input signal for a user A. A replica generator 221 encodes an output signal from the decoder 211 to generate a replica signal for the user A. An adder 231 subtracts the replica signal for the user A generated by the replica generator 221 from the input signal. A decoder 212 applies error correction decoding to an output signal from the adder 231 for a user B. A replica generator 222 encodes an output signal from the decoder 212 to generate a replica signal for the user B. An adder 232 subtracts the replica signal for the user B generated by the replica generator 222 from an output signal from a delay device 202.
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申请公布号 |
JP2001333052(A) |
申请公布日期 |
2001.11.30 |
申请号 |
JP20000148496 |
申请日期 |
2000.05.19 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
UESUGI MITSURU |
分类号 |
G06F11/10;H03M13/13;H03M13/27;H03M13/29;H04L1/00;H04L27/00;(IPC1-7):H04L1/00 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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