| 摘要 |
PROBLEM TO BE SOLVED: To provide an image processor for realizing fast image processing by obtaining a high cache hit ratio in the image processing accelerating a memory access. SOLUTION: When read access is performed from an arithmetic unit 21, a hit discriminating circuit 9 discriminates whether it is cache hit or not in accordance with a memory address. When the cache entry is pre-fetched one as the result of this discrimination, a pre-fetching effect calculation circuit 14 discriminates whether pre-fetching is effective or not. With the result of this discrimination and designation by a pre-fetching designation register 15, a cache control circuit 5 decides whether or not to perform pre-fetching. In the case of performing pre-fetching, a multiplexer 6 is controlled by the value of the register 15 and an adder 17 adds either of a pixel width designation register 3 or a cache line offset 4 with a last-time reference address latched in an address latch 2 to obtain the address of a pre-fetching destination.
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