METHOD AND DEVICE FOR SIMULATION

摘要

PROBLEM TO BE SOLVED: To solve the problem that simulation in function and logic verification of an LSI is performed by using plural test vectors which sometimes have sharable parts such as initialization patterns of a circuit, however, the patterns can not be shared by a conventional simulation method and simulation time becomes wasteful. SOLUTION: The simulation time is put back to a halfway point by a circuit state output processing part 5 which stores a circuit state halfway in simulation separately from test vector information and a circuit state read-in processing part 7 which reads in its circuit state output result and a test vector is changed to shorten the simulation time of a common pattern.