| 摘要 |
PROBLEM TO BE SOLVED: To provide a controller capable of holding optimal data fetch timing, even if various fluctuation factors exist in the controller connected with a semiconductor memory device. SOLUTION: This memory controller connected with a memory to output data with double data rate together with a strobe signal and to control the memory includes a clock signal generation circuit to generate a clock signal to be supplied to the memory and the data fetch circuit to delay the strobe signal by feedback control, so as to be delayed by a time equivalent to approximately a quarter cycle of the clock signal and to latch data by using the delayed strobe signal as a timing signal.
|
