| 摘要 |
<p>A reconfigurable memory (10, 50, 100) having M bit lines (12) and a plurality of row lines (13), where M>1. The memory includes an array (11) of memory storage cells (15), each memory storage cell (15) storing a data value. The data value is read from or into the storage cells by coupling that data value to one of the bit lines (12) in response to a row control signal on one of the row lines (13). A row select circuit (14) generates the row control signal on one of the row lines (13) in response to a row address being coupled to the row select circuit (14). the row select circuit (14) includes a memory for storing a mapping of the row addresses to the row lines (13) that determines which of the row lines (13) is selected for each possible value of the row address. The memory includes a plurality of sense amplifiers, one such sense amplifier being connected to each of the bit lines (12) for measuring a signal value on that bit line (12). A controller (40) that is part of the memory tests the memory storage cells (15) both at power up and run time to detect defective memory storage cells (15). The controller (40) uses an error correcting code scheme to detect errors during the actual operation of the memory. The memory includes sufficient spare rows and columns to allow the controller (40) to substitute spares for rows or columns having defective memory storage cells (15).</p> |
