Semiconducting memory for high speed operation has word drive circuit driving word line in response to word reset signal, main word signal and word decoder signal

摘要

The device has a block selection circuit (101) that outputs a block selection signal on the basis of an address signal, a word reset circuit (107) that outputs a word reset signal on the basis of the block selection signal and a word drive circuit (114) that drives a word line in response to the word reset signal, a main word signal indicating selection of the word drive circuit and a word decoder signal indicating selection of the word line. Independent claims are also included for the following: a method of driving a word line.