EEPROM WITH ERASING GATE ADJACENT FLOATING GATE AND CONTROL GATE

摘要

A structure of a floating gate type EEPROM capable of implementing micromachining less than submicron and a method for fabricating it are disclosed. Since a silicon oxide film 3 for element isolation is embedded in an P-type Si substrate 1, as compared with the case where the element isolation region is formed on the P-type Si substrate 1, a level difference between the P-type Si substrate 1 and a floating gate electrode 6, control gate electrode 8 and erasing gate electrode 12 can be reduced remarkably. This solves a problem of etching remainder during the dry etching of each electrode. In addition, the depth of focus in lithography can be easily assured. This realizes a floating gate type EEPROM equipped with an erasing gate which is so fine as to be less than submicron.