| 摘要 |
A method for forming a high-speed device in an integrated circuit is disclosed. The approaches include reduction of gate-size and cutback on device capacitance and resistance. In the present invention, poly-trench etching followed by silicone selective growth and dielectric spacer formation are used to define gate length. A reduced gate size is therefore obtained. As with a dielectric buffer layer positioned below the source and drain regions, the proposed device possesses a largely decreased junction capacitance area. The design of air-gap spacer is to cut down on the overlap capacitance between gate and source/drain. Finally, with the application of raised polysilicon source and drain layers to behave as silicide consumption layer and the utilization of the buffer layer to provide diffusion protection, the silicide layer can be thickly formed to reduce sheet resistance without any increment on the junction leakage current.
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