| 摘要 |
A system and method for forming a memory having at least 16 megabits (224 bits) and only a single deposition layer of highly conductive interconnects. The resulting semiconductor die or chip fits within existing industry-standard packages with little or no speed loss over previous double metal deposition layered DRAM physical architectures. This is accomplished using a die orientation that allows for a fast single metal speed path. The architecture can be easily replicated to provide larger size memory devices. In addition, a method is described for reducing parasitic resistance in an n-sense amplifier.
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